High performance silicon condenser microphone with perforated single crystal silicon backplate

ABSTRACT

A silicon condenser microphone is described. The silicon condenser microphone of the present invention comprises a perforated backplate comprising a portion of a single crystal silicon substrate, a support structure formed on the single crystal silicon substrate, and a floating silicon diaphragm supported at its edge by the support structure and lying parallel to the perforated backplate and separated from the perforated backplate by an air gap.

TECHNICAL FIELD

The invention relates to a method of manufacturing a silicon condensermicrophone, and more particularly, to a method of manufacturing a highperformance silicon condenser microphone using a silicon micro-machiningprocess.

BACKGROUND

Silicon condenser microphones have long been an attractive research anddevelopment subject. Various microphone designs have been invented andconceptualized by using silicon micro-machining technology. Despitevarious structural configurations and materials, the silicon condensermicrophone consists of four basic elements: a movable compliantdiaphragm, a rigid and fixed backplate (which together form a variableair gap capacitor), a voltage bias source, and a pre-amplifier. Thesefour elements fundamentally determine the performance of the condensermicrophone. In pursuit of high performance; i.e., high sensitivity, lowbias, low noise, and wide frequency range, the key design considerationsare to have a large size of diaphragm and a large air gap. The formerwill help increase sensitivity as well as lower electrical noise, andthe later will help reduce acoustic noise of the microphone. However,the large diaphragm requires a large span of anchored supports andcorrespondingly a large backplate. Also, a large air gap requires athick sacrificial layer. These present major difficulties in siliconmicro-machining processes. Due to constraints of material choices andintrinsic stress issues in silicon micro-machining, the siliconmicrophones reported so far have not achieved sensitivity of more than20 mV/Pa.

Miniaturized silicon microphones have been extensively developed forover sixteen years, since the first silicon piezoelectric microphonereported by Royer in 1983. In 1984, Hohm reported the first siliconelectret-type microphone, made with a metallized polymer diaphragm andsilicon backplate. And two years later, he reported the first siliconcondenser microphone made entirely by silicon micro-machiningtechnology. Since then a number of researchers have developed andpublished reports on miniaturized silicon condenser microphones ofvarious structures and performance.

Some of these reports include the following:

-   -   1) D. Hohm and R. Gerhard-Multhaupt, “Silicon-dioxide electret        transducer”, J. Acoust. Soc. Am., Vol. 75, 1984, pp. 1297-1298.    -   2) D. Hohm and G. Hess, “A Subminiature condenser microphone        with silicon nitride membrane and silicon backplate”, J. Acoust.        Soc. Am., Vol. 85, 1989, pp. 476-480.    -   3) Murphy, P. et al., “Subminiature silicon integrated electret        capacitor microphone”, IEEE Trans. Electr. Ins., Vol. 24, 1989,        pp. 495-498.    -   4) Bergqvist, J. et al., “A new condenser microphone in        silicon”, Sensors and Actuators, Vol. A21-23, 1990, pp. 123-125.    -   5) Kuhnel, W. et al., “A Silicon condenser microphone with        structured backplate and silicon nitride membrane,” Sensors and        Actuators, Vol. 30, 1991, pp. 251-258.    -   6) Scheeper, P. R. et al., “Fabrication of silicon condenser        microphones using single wafer technology”, Journal of        Microelectromechanical Systems, Vol. 1, No. 3, 1992, pp.        147-154.    -   7) Scheeper, P. R. et al., “A Review of Silicon Microphones”,        Sensors and Actuators A, Vol. 44, July 1994, pp. 1-11.    -   8) Bergqvist, J. et al., “A Silicon Microphone using bond and        etch-back technology”, Sensors and Actuators A, vol. 45, 1994,        pp. 115-124.    -   9) Zou, Quanbo et al., “Theoretical and experimental studies of        single-chip-processed miniature silicon condenser microphone        with corrugated diaphragm”, Sensors and Actuators A, Vol. 63,        1997, pp. 209-215.    -   10) Brauer, M. et al., “Silicon microphone based on surface and        bulk micromachining”, Journal of Micromech. Microeng., Vol. 11,        2001, pp. 319-322.    -   11) Bergqvist, J. and V. Rudolf, “A silicon condenser microphone        with a highly perforated backplate”, Transducer 91, pp. 266-269.

U.S. Pat. No. 5,870,482 to Loeppert et al reveals a silicon microphone.U.S. Pat. No. 5,490,220 to Loeppert shows a condenser and microphonedevice. U.S. patent application Publication 2002/0067663 to Loeppert etal shows a miniature acoustic transducer. U.S. Pat. No. 6,088,463 toRombach et al teaches a silicon condenser microphone process. U.S. Pat.No. 5,677,965 to Moret et al shows a capacitive transducer. U.S. Pat.Nos. 5,146,435 and 5,452,268 to Bernstein disclose acoustic transducers.U.S. Pat. No. 4,993,072 to Murphy reveals a shielded electrettransducer.

However, none of the silicon condenser microphones mentioned above hasbeen reported to achieve sensitivity above 20 mV/Pa. In terms ofconventional condenser microphones (i.e. non-silicon), very few productscan have sensitivity as high as 100 mV/Pa. For example, Bruel & Kjoer,Denmark (B&K) has only one microphone available with this highsensitivity (B&K 4179, 1-inch diameter). Its dynamic range is about 140dB (200 Pa) and frequency range is 5-7 kHz. However, this microphonemust be fit onto a bulky pre-amplifier and requires a polarizationvoltage of 200V

SUMMARY OF THE INVENTION

A principal object of the present invention is to provide an effectiveand very manufacturable method of fabricating a silicon condensermicrophone having high sensitivity and low noise.

Another object of the invention is to provide a silicon condensermicrophone design having high sensitivity and low noise.

A further object of the invention is to provide a method for fabricatinga silicon condenser microphone using via contact processes for a planarprocess.

Yet another object of the invention is to provide a method forfabricating a silicon condenser microphone using buckling of a compositediaphragm to prevent stiction in a wet release process.

In accordance with the objects of this invention a silicon condensermicrophone is achieved. The silicon condenser microphone of the presentinvention comprises a perforated backplate comprising a portion of asingle crystal silicon substrate, a support structure formed on thesingle crystal silicon substrate, and a floating silicon diaphragmsupported at its edge by the support structure and lying parallel to theperforated backplate and separated from the perforated backplate by anair gap.

Also in accordance with the objects of this invention a method offabricating a silicon condenser microphone having high sensitivity andlow noise is achieved. A single crystal silicon substrate (P−) isprovided. First ions (P+) of a first conductivity type are implantedinto the single crystal silicon substrate to form a pattern of acousticholes in a central portion of the substrate. Second ions (N−) of asecond conductivity type opposite the first conductivity type areimplanted into the substrate and surrounding the pattern of acousticholes to form a backplate region. Third ions (P+) of the firstconductivity type are implanted overlying the pattern of acoustic holes.Fourth ions (N+) of the second conductivity type are implanted overlyinga portion of the backplate region not surrounding the pattern ofacoustic holes to form an ohmic contact region. A front side nitridelayer is deposited overlying the backplate region. A back side nitridelayer is deposited on an opposite surface of the substrate. A front sidesacrificial oxide layer is deposited overlying the front side nitridelayer. A back side sacrificial oxide layer is deposited overlying theback side nitride layer. First trenches are etched through the frontside sacrificial oxide layer to the ohmic contacts, and to the substrateoff the backplate region. The first trenches are filled with a firstpolysilicon layer which is patterned to form polysilicon caps overlyingthe first trenches and to form polysilicon endplates surrounding thepattern of acoustic holes. A first oxide layer is deposited overlyingthe patterned first polysilicon layer. The first oxide layer is etchedto the polysilicon layer followed by a thin oxide deposition to form thetiny holes for first dimples overlying the endplates. A secondpolysilicon layer is deposited overlying the first oxide layer andfilling the first dimple holes. The second polysilicon layer is etchedto form a functional layer of a composite diaphragm and its lead-out toa bond pad. A second oxide layer is deposited overlying the first oxidelayer and the functional diaphragm. A narrow and continuous opening onthe second oxide layer is etched on an inner edge of the functionaldiaphragm. A third polysilicon layer is deposited overlying the secondoxide layer and filling the openings whereby a portion of the secondoxide layer is enclosed between the second and third polysilicon layersto form a compressive layer of the composite diaphragm. The thirdpolysilicon layer is patterned to remain filling the narrow andcontinuous opening to form a protective layer over the compressive layerof the composite diaphragm. The first and second oxide layers are etchedfollowed by a thin oxide deposition to form second dimple holesoverlying the first dimples. A deep oxide trench etching is made throughthe endplates and the sacrificial oxide layer to the substrate to formthe supporting struts. The first and second oxide layers are etched tomake anchor openings to the polysilicon caps, endplates, and bond pads.A nitride layer is deposited overlying the second oxide layer andfilling the second dimple holes, the oxide trenches and the anchoropenings. The nitride layer is patterned to expose the bond pads and thecomposite diaphragm within the second dimples. Thereafter, the backsidesacrificial oxide layer is removed and the backside nitride layer ispatterned. From the backside, the silicon substrate is etched away tothe backplate region. The pattern of acoustic holes is selectivelyetched away. The backside nitride layer and the frontside nitride layerexposed by the acoustic holes are etched away from the backside. Thefrontside sacrificial oxide layer is removed using a wet etching methodwherein the compressive layer of the composite diaphragm causes thecomposite diaphragm to buckle in a direction away from the backplateregion. After drying, the protective layer and the compressive layer ofthe composite diaphragm are removed wherein the functional diaphragmflattens to complete fabrication of a silicon condenser microphone.

BRIEF DESCRIPTION OF THE DRAWINGS

In the accompanying drawings forming a material part of thisdescription, there is shown:

FIGS. 1 through 20 schematically illustrate in cross-sectionalrepresentation a preferred embodiment of the present invention.

FIG. 21 schematically illustrates in cross-sectional representation acompleted microphone of the present invention.

FIG. 22 graphically illustrates a typical simulated frequency responsefor a microphone of the present invention.

FIG. 23 graphically illustrates simulated and tested frequency responsesfor a microphone of the present invention.

FIG. 24 graphically illustrates the tested equivalent noise level for amicrophone of the present invention.

FIG. 25 graphically illustrates tested frequency responses for amicrophone of the present invention.

DESCRIPTION OF THE PREFERRED EMBODIMENTS

The present invention discloses a novel design and process for making asilicon condenser microphone. Referring now more particularly to FIG. 1,there is shown a semiconductor substrate 10, preferably composed ofP-doped monocrystalline silicon. A thermal oxide layer 12 is grown onthe surface of the substrate to a thickness of between about 270 and 330Angstroms.

Referring now to FIG. 2, P+ implants 16 are made through a mask, notshown. These implanted regions 16 will form acoustic holes on thebackplate in the later selective silicon etching process. The P+ implantcondition must ensure the acoustic hole size at a desired backplatethickness. Now, an N− implanted region 18 is formed using a second mask,not shown. The N− implant condition must ensure a low stress backplateso that the backplate will not deform after the release process at theend of the fabrication process. The implanted ions are driven in to adepth of about 10 microns, which is the depth of the N− region. Becauseof the dosage difference, the P+ region has a larger drive-in depth.

The thermal oxide layer 12 is removed, for example, by wet etching. Nowa second thermal oxide layer 20 is grown on the surface of the substrateto a thickness of between about 270 and 330 Angstroms, as illustrated inFIG. 3. A P++ implantation region 22 is formed at the surface of thesubstrate using a PMOS source/drain implant condition. A N++implantation region 24 is formed elsewhere at the surface of thesubstrate using an NMOS source/drain implant condition. A backside P++implantation region 26 is formed on the backside of the wafer using aPMOS source/drain implant condition. Now, a shallow drive-insource/drain annealing is performed and the thermal oxide layer 20 isremoved.

Referring now to FIG. 4, a composite dielectric layer is formed on frontand back sides of the wafer. First a thermal oxide layer is grown on thefront and back sides (illustrated as top and bottom of the drawingfigure) to a thickness of between about 270 and 330 Angstroms. Next, asilicon nitride layer is deposited by low pressure chemical vapordeposition (LPCVD) over the thermal oxide layer on the front and backsides of the wafer to a thickness of between about 1400 and 1600Angstroms. The composite oxide/nitride layer 30 is patterned to exposethe P++ contact on the wafer edge. The composite oxide/nitride layerwill act as an etching stop on the frontside and as a silicon etchingmask on the backside.

Now, a tetraethoxysilane (TEOS) oxide layer is deposited over thecomposite oxide/nitride layer on both the front and back sides of thewafer by LPCVD to a thickness of between about 1800 and 2200 Angstroms.Finally, a second nitride layer is deposited over the TEOS layer only onthe back side of the wafer by plasma enhanced chemical vapor deposition(PECVD). This will provide an excellent mask for silicon etching by KOHon the backside of the wafer. The composite layer of thermal oxide,nitride, and TEOS oxide on the top side of the wafer is represented by30 in FIG. 4. The composite layer of thermal oxide, nitride, TEOS oxide,and PECVD nitride on the back side of the wafer is represented by 32.

Now, sacrificial oxide layers are deposited on the front and back sidesof the wafer as shown in FIG. 5. The oxide layer on the back side of thewafer provides stress balance. Sacrificial oxide layers 40 and 42 may beformed in successive steps. For example, a first layer ofphosphosilicate glass (PSG) is deposited on the front side of the waferto a thickness of about 3 microns, followed by a TEOS oxide layerdeposited by PECVD to a thickness of about 1 micron. Next, a 3 micronlayer of PSG and a successive 1 micron layer of PE-TEOS is deposited onthe back side of the wafer. Then, a 2 μm layer of PSG is deposited onthe PE-TEOS layer on the front side of the wafer, followed by 1 μm ofPE-TEOS and 1 μm of PSG. This completes the front side sacrificial oxidelayer 40. The backside sacrificial oxide layer 42 may be completed inthe same way by depositing a 2 μm layer of PSG is deposited on thePE-TEOS layer on the back side of the wafer, followed by 1 μm of PE-TEOSand 1 μm of PSG. Other combinations of steps and materials can be used.The wafer is annealed; for example, at between about 950 and 1150° C.for about 30 minutes. The annealing serves to densify the compositesacrificial oxide layer.

Referring now to FIG. 6, deep trenches are etched through thesacrificial oxide layer 40 and the composite dielectric layer 30 to thesilicon substrate.

Now, a polysilicon layer 46 is deposited over the top oxide layer andwithin the trenches. Simultaneously, polysilicon 48 is deposited on thebottom oxide layer 42. The polysilicon layer is patterned to leave apolysilicon cap of about 1.5 μm in thickness over the filled trenchesand elsewhere as shown in FIG. 7. The filled trenches provide viacontacts to the N-type doped backplate as well as the isolation walls toprotect the oxide outside the diaphragm area. The caps are formed toprovide supports for the diaphragm. Now the wafer is annealed; forexample, at between about 950 and 1150° C. for about 90 minutes. Thisannealing causes the polysilicon 46 to be doped by the phosphorouscomponent in the PSG.

Now the diaphragm is to be formed. An oxide layer 50 is deposited overthe patterned polysilicon layer, as shown in FIG. 8. For example, theoxide layer 50 may comprise a first layer of TEOS oxide deposited byLPCVD to a thickness of between about 900 and 1100 Angstroms and asecond layer of PSG oxide having a thickness of between about 8100 and9900 Angstroms. The LP-TEOS layer is necessary to prevent PSG frombubbling and serious reflow in later high temperature annealing steps.Other materials like PE-TEOS oxide may also be used. Now, the oxidelayer 50 is etched to the polysilicon layer 46 above the acoustic holes16. A thin oxide layer, not shown, is deposited conformally over theoxide layer 50 to a thickness of between about 900 and 1100 Angstromsand lining the holes etched to the polysilicon layer to form dimpleholes 53. Oxide layer 50 includes this additional thin oxide layer inthe drawing figures.

Now a layer of polysilicon 58 is deposited over the oxide layer 50 andfilling the dimple holes to form the dimples 53, as shown in FIG. 10.The thickness of the polysilicon layer should be about 3 μm. Thepolysilicon layer 58 is patterned as shown. The section 59 is a lead-outto a bond pad.

As illustrated in FIG. 11, a PSG layer 60 is deposited over the oxidelayer 50 and the polysilicon layer 58 to a thickness of between about4500 and 5500 Angstroms. A narrow and continuous opening is etchedthrough the PSG layer 60 to the polysilicon layer 58. A polysiliconlayer 62 is deposited over the PSG layer and filling the opening, asshown in FIG. 12. The polysilicon layer 62 has a thickness of betweenabout 3500 and 4100 Angstroms. The polysilicon layer 62 encloses the PSGlayer overlying the polysilicon layer 58.

Referring now to FIG. 13, the oxide layer 60 is etched to form dimpleholes 65 directly overlying the dimple holes 53 filled with thediaphragm layer 58. Another oxide layer is deposited over the oxidelayer 60 and lining the dimple holes 65. This oxide layer is not shownapart from the oxide layer 60 in the drawings. Because of this oxidelayer, the dimples do not contact the diaphragm layer 58. Deep trenches67 are etched through the oxide layer 60, the polysilicon layer 46, andthe oxide layer 40 to the silicon substrate adjacent to but outside theedges of the diaphragm 58. Anchor openings 69 are also etched,preferably using a wet etching recipe, to the horizontal polysiliconstructures 46 overlying the first deep trenches filled with polysilicon46 and overlying the second deep trenches 67. A wet etching recipe ispreferred so that a sloped opening is formed. The sloped opening willprevent sharp corners in a later nitride deposition.

As illustrated in FIG. 14, a nitride layer 70 is deposited over thewafer and filling the dimple holes 65, trenches 67, and openings 69. Thenitride layer is deposited by PECVD for low tensile stress to athickness of about 3 μm. The nitride layer 72 within the deep trenches67 forms supporting struts for the diaphragm. The nitride layer 74within the anchor openings 69 forms anchors.

The nitride layer 70 is etched using, for example, a combination of dryand wet etching to form openings 75 to bonding pads 46 and 59 and toclear the nitride from the area of the diaphragm.

A contact 81 is opened by a dry and wet etching process to the substratesurface, as shown in FIG. 15. The etching is made on the wafer edge toopen the contact to the P++ region which connects all P+ acoustic holes.A chromium layer is deposited over the substrate to a thickness ofbetween about 700 and 900 Angstroms followed by a gold seed layer havinga thickness of between about 2200 and 2600 Angstroms. Gold iselectroplated selectively onto the seed layer to form bond pads 83having a thickness of about 2 μm.

Referring now to FIG. 16, layers 48 and 42 are stripped from thebackside of the wafer. Then, layer 32 is etched away where it is notcovered by a mask, not shown, using a nitride etching recipe.

Now, a KOH etching is performed using the composite layer 32 as mask, toopen the back side of the wafer as shown in FIG. 17. The etching is aselective etching of silicon using a four electrode electro-chemicaletching (ECE) configuration. The N− region contacts a positive electrode(working electrode) while the P+ acoustic hole region connects to anegative electrode (cathode). A negative electrode (counterelectrode) isinserted in the KOH solution. A reference electrode in the KOH solutionprovides the referential potential. By the four-electrode configuration,the N− region and the p-type substrate are inverse biased. The siliconis etched until the N− region is reached. The sudden increased currentin the N− region causes oxide passivation to prevent N− from beingetched. The etching continues at the P+ acoustic holes because of thereverse biasing. The potentials of all the electrodes are required to becontrolled properly. This is the key to the ECE technique. Etching stopsat the nitride in layer 30. Back side opening 91 is shown.

Cr/Au as the sputtered ECE metal layer is etched. 83 is plated by Auabout 2 microns thick and so remains. A blanket nitride stripping fromthe back side of the wafer removes layer 32 completely and also stripsnitride layer 30 where it is exposed by the acoustic holes, asillustrated in FIG. 18.

The wafer is now cut by a high speed spinning diamond cutter, calleddicing. Now, the wafer is subjected to a dip in a hydrofluoric acidsolution, preferably about 49% HF, for about 3.5 minutes. This dipremoves the sacrificial oxide layer 40 through the backside opening aswell as the frontside gaps, as shown in FIG. 19.

FIG. 19 shows compressive buckling of the diaphragm 58. The sandwichedcompressive layer 60 causes buckling during the wet release step. Thiscompressive buckling is desirable as it can counter the stiction forceduring drying and thus prevent the diaphragm from sticking to thebackplate 100. The device is rinsed and then dried. For example, rinsingis in de-ionized water for about 30 minutes and in methanol for 30minutes. Drying is done in an oven at 90° C. The dimples 58 are there tominimize the constraints to the diaphragm for the desiredsimply-supported boundary condition. Dimples can touch either to thepoly caps 46 or to the top nitride 70.

Now, the protective layer 62 and the compressive layer 60 of thecomposite diaphragm are removed. First the polysilicon layer 62 isremoved by a dry etching. A second dry etching step removes the PSGoxide layer 60. No masking is required in these removal steps becauseeither polysilicon etching or oxide etching does not attack the otherexposed layers. The two dry etching process steps have high selectivityto each other.

The completed microphone is shown in FIG. 20. After the compressiveoxide is removed, the stress is released and the diaphragm flattened.

A number of design variations are proposed to cover the sensitivity from25 mV/Pa to above 100 mV/Pa. FIG. 21 and Table I illustrate themicrophone design parameters and Table II illustrates simulatedperformance parameters. In FIG. 21, the die size E is 3980 μm. E isvariable and could be smaller for a smaller diaphragm, for example.Diaphragm size A, air gap B, acoustic hole size C, and acoustic holepitch D are illustrated. TABLE I Design Variations 1 2 3 4 5 Diaphragm2000 1000 1000 2000 2000 size (μm) Diaphragm 3 2 2 2 2 thickness (μm)Air Gap 8 8 8 8 8 (μm) Backplate 10 10 10 10 10 thickness (μm) Acoustic20 30 40 40 40 hole (μm) Acoustic 60 84 100 100 84 hole pitch (μm) #acous. 850 95 75 300 425 holes Acoustic 10.80% 10.90% 15.30% 15.20%12.20% perforation

TABLE II Design Variations 1 2 3 4 5 Zero-bias 3.10 0.80 0.74 2.95 3.48capac. (pF) Collapse 15.6 33.41 34.89 16.69 15.74 voltage (V) Bias volt.(V) 10.4 22.27 23.27 10.69 10.49 Sensitivity −19.63 −31.89 −29.43 −19.7−19.71 dB ref 1 V/Pa Sensitivity 104 25 34 103 103 mV/Pa Low roll-off 3<3 <3 4 4 (Hz) High roll-off 3600 10,000 9000 6500 6600 (Hz) Overpressure 52 247 252 52 52 (Pa)

Table I illustrates design parameter variations that have been reducedto practice for 5 sample dies. Table II illustrates the simulationresults for the 5 sample dies. Important results are the bias voltage(=2/3 of the collapse voltage) and Sensitivity in mV/Pa. Over pressureis shown where deflection is less than 2/3 of the gap height. The designparameters of design variations 1, 4, and 5 enable high sensitivitiesabove 100 mV/Pa while those of design variations 2 and 3 give lowersensitivities (33 mV/Pa) but a wider frequency response.

FIG. 22 illustrates a typical frequency response for design variationnumber 4 with a bias voltage of 10.7 volts. The present invention hasbeen reduced to practice. FIG. 23 provides a simulation and testcorrelation at a bias voltage of 10 volts. Line 231 shows the simulatedresults for a microphone of the present invention. Line 232 shows theactual tested frequency response of a microphone fabricated according tothe process of the present invention. FIG. 24 illustrates the testedequivalent noise level of a microphone fabricated according to theprocess of the present invention at a bias voltage of 10 volts. Theequivalent noise level (ENL) is equal to the microphone self-noisedivided by the microphone sensitivity. The ENL decides the minimum soundpressure level that can be detected by the microphone. The tested ENL inFIG. 24 was 9.4 dBA.

FIG. 25 illustrates tested frequency responses for a microphonefabricated according to the process of the present invention at a biasvoltage of 8 volts showing a sensitivity of 25 mV/Pa. The test resultsshown in these graphs have proven that the invented microphone designand fabrication method can produce the microphone with any desired highperformance—higher sensitivity (>100 mV/Pa) in a narrow frequency range(<3 KHz) or lower sensitivity (>20 mV/Pa) in a wider frequency range(>10 KHz).

The microphone design and fabrication process of the present inventionproduces a high performance microphone with the highest sensitivity andlowest noise achieved. The microphone of the present invention includesa stress-free polysilicon diaphragm. The composite diaphragm designincludes compressive buckling for anti-stiction. After release anddrying, the compressive layers on the diaphragm are removed. Thefabrication process is a planar process despite thick sacrificiallayers. Via contacts are formed by polysilicon filling and self-doping.

While the invention has been particularly shown and described withreference to the preferred embodiments thereof, it will be understood bythose skilled in the art that various changes in form and details may bemade without departing from the spirit and scope of the invention.

1. A method of fabricating a perforated silicon diaphragm comprising:providing a single crystal silicon substrate of a first conductivitytype; blanket implanting first ions of a second conductivity typeopposite said first conductivity type into said single crystal siliconsubstrate to form an etch stop layer; selectively implanting second ionsof said first conductivity type into said single crystal siliconsubstrate to form a pattern of holes in a portion of said substrate;implanting third ions of said first conductivity type overlying saidpattern of holes and forming a first ohmic contact region; implantingfourth ions of said second conductivity type not surrounding saidpattern of holes to form a second ohmic contact region; thereafterdepositing a nitride layer on a frontside and a backside of said siliconsubstrate; forming contacts through said nitride layer to said first andsecond ohmic contact regions; thereafter patterning said backsidenitride layer; and from the backside, etching away said siliconsubstrate not covered by said nitride layer to said etch stop layer andsimultaneously selectively etching away said pattern of holes tocomplete formation of said perforated diaphragm.
 2. The method accordingto claim 1 wherein said first conductivity type is P-type and whereinsaid second conductivity type is N-type.
 3. The method according toclaim 1 wherein said first ions are N− ions, said second ions are P+ions, said third ions are P++ ions, and said fourth ions are N++ ions.4. The method according to claim 1 wherein said nitride layer isdeposited by low pressure chemical vapor deposition.
 5. The methodaccording to claim 1 wherein said nitride layer has a thickness ofbetween about 1000 and 1500 Angstroms.
 6. The method according to claim1 wherein said etch stop layer has a depth into said silicon substrateof between about 1 and 10 microns.
 7. The method according to claim 1wherein said step of forming contacts through said nitride layer to saidfirst and second ohmic contact regions comprises: etching contactopenings through said nitride layer to said first and second ohmiccontact regions; depositing a metal layer within said contact openingsand overlying said nitride layer; and patterning said metal layer toform a first electrode contacting said first ohmic contact region and asecond electrode contacting said second ohmic contact region.
 8. Themethod according to claim 1 wherein said step of etching away saidsilicon substrate not covered by said nitride layer to said etch stoplayer and simultaneously selectively etching away said pattern of holescomprises KOH with a 4 electrode electrochemical etching (ECE)configuration.
 9. A method of fabricating a perforated silicon diaphragmcomprising: providing a single crystal silicon substrate of a firstconductivity type; blanket implanting first ions of a secondconductivity type opposite said first conductivity type into said singlecrystal silicon substrate to form an etch stop layer wherein a depth ofsaid etch stop layer into said silicon substrate determines a thicknessof said perforated diaphragm; selectively implanting second ions of saidfirst conductivity type into said single crystal silicon substrate toform a pattern of holes in a portion of said substrate; implanting thirdions of said first conductivity type overlying said pattern of holes andforming a first ohmic contact region; implanting fourth ions of saidsecond conductivity type not surrounding said pattern of holes to form asecond ohmic contact region; thereafter depositing a nitride layer on afrontside and a backside of said silicon substrate; forming contactsthrough said nitride layer to said first and second ohmic contactregions; thereafter patterning said backside nitride layer; and from thebackside, etching away said silicon substrate not covered by saidnitride layer to said etch stop layer and simultaneously selectivelyetching away said pattern of holes to complete formation of saidperforated diaphragm.
 10. The method according to claim 9 wherein saidfirst conductivity type is P-type and wherein said second conductivitytype is N-type.
 11. The method according to claim 9 wherein said firstions are N− ions, said second ions are P+ ions, said third ions are P++ions, and said fourth ions are N++ ions.
 12. The method according toclaim 9 wherein said nitride layer is deposited by low pressure chemicalvapor deposition.
 13. The method according to claim 9 wherein saidnitride layer has a thickness of between about 1000 and 1500 Angstroms.14. The method according to claim 9 wherein said etch stop layer has adepth into said silicon substrate of between about 1 and 10 microns. 15.The method according to claim 9 wherein said step of forming contactsthrough said nitride layer to said first and second ohmic contactregions comprises: etching contact openings through said nitride layerto said first and second ohmic contact regions; depositing a metal layerwithin said contact openings and overlying said nitride layer; andpatterning said metal layer to form a first electrode contacting saidfirst ohmic contact region and a second electrode contacting said secondohmic contact region.
 16. The method according to claim 9 wherein saidstep of etching away said silicon substrate not covered by said nitridelayer to said etch stop layer and simultaneously selectively etchingaway said pattern of holes comprises KOH with a 4 electrodeelectrochemical etching (ECE) configuration.
 17. A method of fabricatinga perforated silicon diaphragm comprising: providing a single crystalsilicon substrate of a first conductivity type; blanket implanting at afirst dose first ions of a second conductivity type opposite said firstconductivity type into said single crystal silicon substrate to form anetch stop layer wherein a depth of said etch stop layer into saidsilicon substrate determines a thickness of said perforated diaphragm;selectively implanting at a second dose second ions of said firstconductivity type into said single crystal silicon substrate to form apattern of holes in a portion of said substrate; implanting at a thirddose third ions of said first conductivity type overlying said patternof holes and forming a first ohmic contact region; implanting at afourth dose fourth ions of said second conductivity type not surroundingsaid pattern of holes to form a second ohmic contact region; thereafterdepositing a nitride layer on a frontside and a backside of said siliconsubstrate; forming contacts through said nitride layer to said first andsecond ohmic contact regions; thereafter patterning said backsidenitride layer; and from the backside, etching away said siliconsubstrate not covered by said nitride layer to said etch stop layer andsimultaneously selectively etching away said pattern of holes tocomplete formation of said perforated diaphragm.
 18. The methodaccording to claim 17 wherein said first dose is lower than the second,third, and fourth doses.
 19. The method according to claim 17 whereinsaid first conductivity type is P-type and wherein said secondconductivity type is N-type.
 20. The method according to claim 17wherein said first ions are N− ions, said second ions are P+ ions, saidthird ions are P++ ions, and said fourth ions are N++ ions.
 21. Themethod according to claim 17 wherein all of said steps up to saidpatterning said backside nitride layer step can be CMOS compatibleprocesses.
 22. The method according to claim 17 wherein, said etch stoplayer has a depth into said silicon substrate of between about 1 and 10microns.
 23. The method according to claim 17 wherein said step offorming contacts through said nitride layer to said first and secondohmic contact regions comprises: etching contact openings through saidnitride layer to said first and second ohmic contact regions; depositinga metal layer within said contact openings and overlying said nitridelayer; and patterning said metal layer to form a first electrodecontacting said first ohmic contact region and a second electrodecontacting said second ohmic contact region.
 24. The method according toclaim 17 wherein said step of etching away said silicon substrate notcovered by said nitride layer to said etch stop layer and simultaneouslyselectively etching away said pattern of holes corn with a 4 electrodeelectrochemical etching (ECE) configuration.
 25. The method according toclaim 23 wherein said step of implanting at a third dose third ions ofsaid first conductivity type overlying said pattern of holes connectssaid pattern of holes together to provide external electric biases forsaid ECE configuration.